FIG. 1 illustrates an example of a configuration of a computer system. This computer system includes system boards (SBs) #0 through #7, input/output units (IOUs) #0 through #7, memory-system interconnection boards 101, and a management board 102.
Each SB #i (i=0 through 7) includes memories 111, central processing units (CPUs) 112, and a chip set 113. Each IOU #i (i=0 through 7) includes a PCI (Peripheral Components Interconnect) cards 131, hard disk devices 132, and a chip set 133.
Each of the memory-system interconnection boards 101 includes a chip set 121, and connects SBs #0 through #7 and IOUs #0 through #7 to each other. The management board 102 includes a controller 141 connected to the respective chip sets 113, 133, and 121, and controls the system. The controller 141 is implemented in the form of, for example, firmware.
The chip sets 113, 133, and 121 are control LSIs (Large Scale Integration). The chip set 113 includes a transmission/reception unit 114, the chip set 121 includes transmission/reception units 122 and 123, and the chip set 133 includes a transmission/reception unit 134. These chip sets are connected to each other via the transmission/reception units, and data is transmitted and received between the chip sets.
FIGS. 2A and 2B illustrate examples of configurations of a transmission chip and a reception chip according to a conventional technique. A transmission chip 201 corresponds to the transmission/reception units on the transmission side, and a reception chip 202 corresponds to the transmission/reception units on the reception side. The transmission chip 201 and the reception chip 202 are connected through a clock signal line and N (N is a positive integer) data signal lines.
The transmission chip 201 includes a phase-locked loop circuit (PLL) 211, a clock output circuit 212, a pattern generation circuit 213, data selection circuits 214-1 through 214-N, flip-flop circuits 215-1 through 215-N and 216-1 through 216-N, bit selection circuits 217-1 through 217-N, data output circuits 218-1 through 218-N, and a transmission-unit control circuit 219.
The transmission-unit control circuit 219 outputs a pattern selection signal to the pattern generation circuit 213 in accordance with a training-starting instruction signal from a controller 141, and outputs a data selection signal to the data selection circuits 214-1 through 214-N.
The PLL 211 generates a clock signal, and outputs the clock signal to the clock output circuit 212, the flip-flop circuits 215-1 through 215-N and 216-1 through 216-N, and the bit selection circuits 217-1 through 217-N. The clock output circuit 212 outputs the clock signal to the reception chip 202.
The pattern generation circuit 213 generates a 2-bit training pattern [1:0] in accordance with the pattern selection signal, and outputs the pattern to the data selection circuits 214-1 through 214-N. A training pattern [1:0] is a data string that is predetermined among the chips, and is used when phases are adjusted.
Each data selection circuit 214-j (j=1 through N) selects either 2-bit transmission data [1:0] or a training pattern [1:0] in accordance with the data selection signal, and outputs the values of bit 0 and bit 1 of the selected signal to the flip-flop circuits 215-j and 216-j, respectively.
Each flip-flop circuit 215-j latches the value of bit zero in synchronization with the clock signal, and outputs the value to the bit selection circuit 217-j. Each flip-flop circuit 216-j latches the value of bit 1 in synchronization with the clock signal, and outputs the value to the bit selection circuit 217-j. 
Each bit selection circuit 217-j selects an output signal from either the flip-flop circuit 215-j or 216-j in accordance with the value of the clock signal, and outputs the signal to the data output circuit 218-j. In this example, when the logic of the clock signal is “1”, the signal output from the flip-flop circuit 215-j is selected, and when the logic of the clock signal is “0”, the signal output from the flip-flop circuit 216-j is selected. Each data output circuit 218-j outputs a signal output from the bit selection circuit 217-j to the reception chip 202 as a data signal.
The reception chip 202 includes a clock input circuit 221, clock adjustment circuits 222-1 through 222-N, clock adjustment control circuits 223-1 through 223-N, pattern detection circuits 224-1 through 224-N, data input circuits 225-1 through 225-N, flip-flop circuits 226-1 through 226-N, 227-1 through 227-N, and 228-1 through 228-N, and a reception-unit control circuit 229.
The reception-unit control circuit 229 outputs a clock adjustment instruction signal to the clock adjustment control circuits 223-1 through 223-N in accordance with the training-starting instruction signal from the controller 141.
A clock signal output from the transmission chip 201 is input to the clock input circuit 221, and the clock input circuit 221 outputs the input clock signal to the clock adjustment circuits 222-1 through 222-N.
Each clock adjustment circuit 222-j delays the phase of the clock signal in accordance with the TAP value j from the clock adjustment control circuit 223-j, generates the adjusted clock signal j, and outputs the adjusted clock signal j to the clock adjustment control circuit 223-j and the flip-flop circuits 226-j, 227-j, and 228-j. 
The data signal output from the data output circuit 218-j in the transmission chip 201 is input to the data input circuit 225-j, and the data input circuit 225-j outputs the input data signal to the flip-flop circuits 226-j and 228-j. 
The flip-flop circuit 226-j latches the data signal in synchronization with the inversion signal of the adjusted clock signal j, and outputs the signal to the flip-flop circuit 227-j. The flip-flop circuit 227-j latches the output signal of the flip-flop circuit 226-j in synchronization with the adjusted clock signal j, and outputs the signal as the value of bit 0 of reception data. The flip-flop circuit 228-j latches the data signal in synchronization with the adjusted clock signal j, and outputs the signal as the value of bit 1 of the reception data. In this manner, 2-bit reception data j [1:0] is generated.
The pattern detection circuit 224-j detects the pattern of reception data j [1:0], and outputs an adjustment pattern detection signal j to the clock adjustment control circuit 223-j, and outputs a termination pattern detection signal j to the reception-unit control circuit 229.
Each clock adjustment control circuit 223-j starts phase adjustment in accordance with the clock adjustment instruction signal, and increases or decreases the TAP value j in accordance with an adjustment pattern detection signal j from the pattern detection circuit 224-j. Then, the clock adjustment control circuit 223-j outputs the TAP value j to the clock adjustment circuit 222-j 
In data transmission between chips, clock signals need to be input to the flip-flop circuits 226-j, 227-j, and 228-j with the edges of the clock signals being made to correspond to the centers of the data waveform in order to secure a margin. Accordingly, phase adjustment of clock signals is usually performed by using a known training pattern [1:0]. When the phase adjustment is performed, the transmission chip 201 selects and outputs a training pattern [1:0]. The reception chip 202 receives a training pattern [1:0] while changing the TAP value j, and calculates the TAP value that corresponds to the center of the data waveform in accordance with the pattern detection result.
FIG. 3 illustrates an example of a configuration of the pattern generation circuit 213 illustrated in FIG. 2A. The pattern generation circuit 213 includes an adjustment pattern storage unit 301, a termination pattern storage unit 302, and a pattern selection circuit 303.
The adjustment pattern storage unit 301 stores 2-bit adjustment pattern “10”, and outputs the adjustment pattern to the pattern selection circuit 303. The termination pattern storage unit 302 stores 2-bit termination pattern “11”, and outputs the termination pattern to the pattern selection circuit 303. The pattern selection circuit 303 selects a pattern in accordance with a pattern selection signal from the transmission-unit control circuit 219, and outputs the selected pattern as a training pattern [1:0].
FIG. 4 illustrates an example of a configuration of the pattern detection circuit 224-j illustrated in FIGS. 2A and 2B. The pattern detection circuit 224-j includes an adjustment pattern storage unit 401, a termination pattern storage unit 402, and comparators 403 and 404.
The adjustment pattern storage unit 401 stores adjustment pattern “10” and outputs the adjustment pattern to the comparator 403. The termination pattern storage unit 302 stores termination pattern “11”, and outputs the termination pattern to the comparator 404.
The comparator 403 compares the reception data j [1:0] and adjustment pattern “10”, and when they correspond to each other, the comparator 403 outputs an adjustment pattern detection signal j (for example, logic “1”) indicating that the pattern detection result is OK. When they do not correspond, an adjustment pattern detection signal (for example, logic “0”) indicating that the pattern detection result is NG is output.
The comparator 404 compares the reception data j [1:0] and termination pattern “10”, and when they correspond to each other, the comparator 404 outputs a termination pattern detection signal j (for example, logic “1”) indicating that the pattern detection result is OK. When they do not correspond, a termination pattern detection signal (for example, logic “0”) indicating that the pattern detection result is NG is output.
FIG. 5 illustrates an example of a configuration of the clock adjustment circuit 222-j illustrated in FIGS. 2A and 2B. The clock adjustment circuit 222-j includes a delay line and a decoder 502. The delay line includes buffer circuits 501-0 through 501-6, switches sw0 through sw6, and capacitors 503-0 through 503-6.
The decoder 502 turns on/off the switches sw0 through sw6 in accordance with the TAP value j from the clock adjustment control circuit 223-j in order to change the load capacity of the delay line. Thereby, the delay amount of the delay line is controlled, and the phases of input clock signals are changed.
FIG. 6 illustrates relationships between TAP values j and switching signals output from the decoder 502 to the switches sw0 through sw6. Switches swk (k=0 through 6) are turned on when an input switching signal has the logic “1”, and are turned off when the logic is “0”. The more switches there are that are turned on, the greater the load capacity and the delay amount become. By contrast, the more switches there are that are turned off, the smaller the load capacity and the delay amount become. In this example, one of eight stages of delay amount can be set by using 3-bit TAP value j [2:0] that expresses one of 0 through 7.
FIG. 7 illustrates an example of a configuration of the clock adjustment control circuit 223-j illustrated in FIGS. 2A and 2B. The clock adjustment control circuit 223-j includes an incrementer 701, a decrementer 702, a TAP value selection circuit 703, flip-flop circuits 704, 705, and 706, an adder circuit 707, a divider circuit 708, and a TAP control circuit 709.
The TAP control circuit 709 starts phase adjustments in accordance with the clock adjustment signal from the reception-unit control circuit 229. Further, the TAP control circuit 709 outputs a TAP value selection signal to the TAP value selection circuit 703 in accordance with an adjustment pattern detection signal j from the pattern detection circuit 224-j, and outputs the TAP value setting signal to the flip-flop circuits 705 and 706.
The incrementer 701 adds 1 to the TAP value output from the flip-flop circuit 704 to output the resultant value to the TAP value selection circuit 703 while the decrementer 702 subtracts 1 from the TAP value output from the flip-flop circuit 704 to output the resultant value to the TAP value selection circuit 703.
The TAP value selection circuit 703 selects one of the TAP values output from the flip-flop circuit 704, the incrementer 701, the decrementer 702, and the divider circuit 708 in accordance with the TAP value selection signal, and outputs the selected the TAP value to the flip-flop circuit 704.
The flip-flop circuit 704 latches a TAP value output from the TAP value selection circuit 703 in synchronization with the adjusted clock signal j, and outputs the value as a TAP value j. The flip-flop circuit 705 latches the TAP value j in synchronization with the adjusted clock signal j, and outputs the value to the adder circuit 707 as the upper limit value. The flip-flop circuit 706 latches the TAP value j in synchronization with the adjusted clock signal j, and outputs the value to the adder circuit 707 as the lower limit value. Also, the flip-flop circuits 705 and 706 hold the upper and lower limit values in accordance with the respective TAP value setting signals.
The adder circuit 707 adds the upper limit value and the lower limit value output from the flip-flop circuit 705 and the flip-flop circuit 706, respectively, and outputs the addition results to the divider circuit 708. The divider circuit 708 outputs to the TAP value selection circuit 703 a value that is half the addition result.
FIG. 8 is a flowchart for operations of the TAP control circuit 709. The TAP control circuit 709 outputs a TAP value selection signal that selects a TAP center value 4 (step S802) in response to reception of a clock adjustment instruction signal from the reception-unit control circuit 229 (step 801).
Next, a pattern detection result is estimated (step 803) on the basis of the adjustment pattern detection signal j from the pattern detection circuit 224-j (step 803). When the pattern detection result is OK, a TAP value selection signal that selects a lower TAP value is output (step 804). Thereby, a TAP value output from the decrementer 702 is output to the clock adjustment circuit 222-j as a TAP value j.
Next, a pattern detection result is determined on the basis of the adjustment pattern detection signal j (step S805), and the operations in step 804 are repeated when the pattern detection result is OK. When the pattern detection result has become NG, the TAP value setting signal is output to the flip-flop circuit 706 (step 808). Thereby, the current TAP value j is set in the flip-flop circuit 706 as the lower limit value.
When the pattern detection result is NG in step 803, a TAP value selection signal that selects a greater TAP value is output (step 806). Thereby, a TAP value output from the incrementer 701 is output to the clock adjustment circuit 222-j as a TAP value j.
Next, the pattern detection result is determined on the basis of the adjustment pattern detection signal (step 807), and the operations in step 806 are repeated when the pattern detection result is NG. When the pattern detection result has become OK, a TAP value setting signal is output to the flip-flop circuit 706 (step 808).
When the lower limit value is set in step 808, a TAP value selection signal that selects a greater TAP value is output (step 809), and a pattern detection result is determined on the basis of the adjustment pattern detection signal j (step 810). When the pattern detection result is OK, the operations in step 809 are repeated. When the pattern detection result has become NG, a TAP value setting signal is output to the flip-flop circuit 705 (step 811). Thereby, the current TAP value j is set in the flip-flop circuit 705 as the upper limit value.
Next, a TAP value selection signal that selects a TAP optimum value is output (step 812). Thereby, the average value between the upper and lower limit values that have been set is selected, and the selected value is output to the clock adjustment circuit 222-j as the TAP value that corresponds to the center of the data waveform.
FIG. 9 is a flowchart for phase adjustment operations performed by the controller 141, the transmission chip 201, and the reception chip 202 illustrated in FIGS. 2A and 2B. The transmission-unit control circuit 219 and the reception-unit control circuit 229 start a phase adjustment in response to an instruction from the external environment when the system is to be initialized, and starts phase adjustments periodically in accordance with a timer when the system is in operation.
When the power of the computer system is turned on (step 901), the controller 141 outputs a training-starting instruction signal to the transmission-unit control circuit 219 and the reception-unit control circuit 229.
The transmission-unit control circuit 219 outputs to the pattern generation circuit 213 a pattern selection signal that selects an adjustment pattern, and outputs to the data selection circuits 214-1 through 214-N the data selection signal that selects a training pattern [1:0]. Thereby, the adjustment pattern is transferred as a training pattern [1:0] to the reception chip 202 (step 902).
The reception-unit control circuit 229 outputs a clock adjustment instruction signal to the clock adjustment control circuits 223-1 through 223-N. Thereby, the operations in FIG. 8 start, and a phase adjustment of a clock signal is performed (step 903).
When the phase adjustment is terminated (step 904), the transmission-unit control circuit 219 outputs to the pattern generation circuit 213 a pattern selection signal that selects a termination pattern, and initializes the timer. Thereby, the termination pattern is transferred as a training pattern [1:0] to the reception chip 202 (step 905).
The pattern detection circuits 224-1 through 224-N output to the reception-unit control circuit 229 termination pattern detection signals 1 through N, which indicate the termination of the phase adjustments, and the reception-unit control circuit 229 initializes the timer (step 906). Thereby, normal operations using the adjusted clock signals 1 through N are performed until the counting operations of the timers of the transmission-unit control circuit 219 and the reception-unit control circuit 229 expire (step 907).
When the counting operations of the timers of the transmission-unit control circuit 219 and the reception-unit control circuit 229 have expired (step 908), the operations in and subsequent to step 902 are repeated. As described above, the transmission-unit control circuit 219 and the reception-unit control circuit 229 perform the operations of steps 902 through 905 not only at the time of initialization but also during operation so as to readjust the phases of clock signals.
FIGS. 10A and 10B are a timing chart illustrating an example of the phase adjustment operations performed by the reception chip 202 illustrated in FIGS. 2A and 2B. When phases are adjusted, adjustment pattern “10” is repeatedly output from the data output circuit 218-j of the transmission chip 201, and repeated patterns such as “010101 . . . ” are input to the data input circuit 225-j of the reception chip 202.
Then, the output waveforms of the clock input circuit 221 and the data input circuit 225-j are as denoted by (1). The operation that is expected to be performed is to receive data “0” at down edges of the clock signal and to receive data “1” at up edges of the clock signal.
When the phase of the clock signal is advanced slightly by the clock adjustment circuit 222-j, the waveforms of the adjusted clock signal j, the reception data j [1], the reception data j [0] (first stage FF), the reception data j [0] (second stage FF), and the adjustment pattern detection signal j are as denoted by (2). The reception data j [1] expresses the signal output from the flip-flop circuit 228-j, and the reception data j [0] (first stage FF) and the reception data j [0] (second stage FF) express the signals output from the flip-flop circuits 226-j and 227-j, respectively.
In such a case, the flip-flop circuit 226-j receives data “0” at down edges of the adjusted clock signal j, and the flip-flop circuit 228-j receives data “1” at up edges of the adjusted clock signal j. Accordingly, the reception data j [1:0] corresponds to adjustment pattern “10”. Accordingly, the adjustment pattern detection signal j indicates OK.
When the phase of the clock signal is advanced further by the clock adjustment circuit 222-j, the waveforms of the respective signals become as denoted by (3). In such a case, the down edges of the adjusted clock signal j come earlier than data “0”, and data “1” is received at the down edges. Similarly, the up edges of the adjusted clock signal j come earlier than data “1”, and data “0” is received at up edges. Due to this, the reception data j [1:0] becomes “01”, which does not correspond to adjustment pattern “10”. Thus, the adjustment pattern detection signal j indicates NG.
When the phase of the clock signal is delayed by the clock adjustment circuit 222-j, the waveforms of the respective signals become as denoted by (4). In such a case, the down edges of the adjusted clock signal j come later than data “0”, and data “1” is received at the down edges. Similarly, the up edges of the adjusted clock signal j come later than data “1”, and data “0” is received at the up edges. Due to this, the reception data j [1:0] becomes “01”, which does not correspond to adjustment pattern “10”. Thus, the adjustment pattern detection signal j indicates NG.
As denoted by (1) through (4), the reception data [1:0] and adjustment pattern “10” are compared to each other while the clock adjustment circuit 222-j changes the phase of the clock signal, and thereby the pattern detection result (OK or NG) is determined for each phase. The center value of the range of TAP values for which the pattern detection result is OK corresponds to the center of the data waveform, and the phase adjustment is completed by calculating the center value. The waveforms of the respective signals after the completion of the phase adjustment become as denoted by (5).
In addition to the above described phase adjustments of clock signals, a technique of correcting phases between bits of parallel data is known (see Patent Documents 1 and 2, for example).
However, the above described conventional methods of adjusting a phase involve problems, as below.
(1) Relationships in phase between clock signals and data signals are changed as time elapses due to temperature variations, power source voltage variations, clock variations caused by jitter in PLL, etc., and accordingly the phases gradually shift from the optimum phase. This makes it necessary to conduct readjustments, even during the system operation, before phases are shifted so greatly as to prevent the signal transmission. A phase adjustment requires the transmission of a training pattern with normal data transmissions being halted temporarily, which deteriorates the data transfer performance. In particular, when the transmission speed is high, readjustments need to be conducted highly frequently, which greatly influences the data transfer performance.
(2) As has been described, because phase adjustments are conducted only periodically, edges of a clock signal do not always follow the center of the data waveforms, and shifts to some extent need to be tolerated. This increases the frequency of occurrences of errors when relationships in the phases of clock signals and data signals change greatly.    Patent Document 1: Japanese Laid-open Patent Publication No. 5-145537    Patent Document 2: Japanese National Publication of International Patent Application No. 2004-531117